1. Field of the Invention
This invention relates generally to the method of reading and writing memory devices and more particularly to the control flow and timing waveforms of read and write operations for accessing memory devices.
2. Description of Related Art
Nonvolatile memory (NVM) and volatile memory (VM) are well known in the art. The different types of nonvolatile memory include read-only-memory (ROM), electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), NOR flash, and NAND flash. In current applications such as personal digital assistants, cellular telephones, notebook and laptop computers, voice recorders, global positioning systems, etc., the flash memory has become one of the more popular types of nonvolatile memory. Flash memory has the combined advantages of high density, small silicon area, low cost and can be repeatedly programmed and erased with a single low-voltage power supply voltage source and faster speed.
Currently, the mobile market and application demands are toward very high speed, power-saving, high-density and low cost memory chips, regardless of VM and NVM. In the lower end cell phone market, a multi-chip package (MCP) combo memory with 32 Mb serial NOR flash and 16 Mb SRAM is commonly used. In the middle end of higher density cell phone market, another kind of MCP combo memory with 128 Mb parallel NOR flash and 64 Mb pSRAM is extensively used. In contrast, in the highest end smart phone market, the 3rd kind of MCP combo memory with 32 Gb multi-level cell (MLC) NAND flash and 4 Gb DRAM has become the mainstream highest storage solution in 2010 and beyond.
The NAND flash, which is a slow serial access memory, is commonly used as a low-cost and extremely high-density audio and video data storage device. In 2010, the NAND flash density has achieved 64 Gb MLC per die made by 2×nm technology nodes. NAND flash uses FN-tunneling scheme to perform fast but low current block erase and page program operations. NAND flash is commonly encapsulated in a 48 pin package with x8 or x16 I/O pins. The most advanced node of NAND technology in production used 20 nm technology in 2010.
There are two kinds of NOR flash. One is parallel NOR and the other is serial NOR. The parallel NOR flash, which is a fast random access memory, is commonly used as a low-cost, high-density code and application program storage device. In 2010, the parallel NOR flash density has achieved only 2 Gb MLC per die made by 45 nm technology nodes. The parallel NOR flash today uses FN-tunneling scheme to perform slow block or sector erase operations but uses high current channel-hot-electron (CHE) scheme for fast byte or word program operations.
The extremely high density parallel NOR flash is available in both 56 pin and 48 pin packages, while the serial NOR is in 8 pin serial peripheral interface (SPI) or serial quad I/O (SQI) packages. The most advanced node of NOR flash technology in production used 65 nm technology in 2010.
The unique feature of EEPROM is its in-system or in-circuit low current fast re-programmability with superior 1M endurance program and erase cycles. The EEPROM is commonly used in frequently updated small byte alterable data storage in contact and contactless applications such as Smart-card, SIM-card, Bank-card and ePassport ICs, etc. It employs FN-tunneling scheme like NAND flash to perform both program and erase operations in unit of byte or page.
Unlike EPROM, two key program and erase operations of EEPROM can be performed after the sealing of the package. Due to the limitations in its largest cell size and poorest cell scalability among all NVM, the most advanced EEPROM technology node in production has used 0.15 um technology since 2010 with maximum available density of 2 Mb for embedded parallel read design but serial read in standalone 8-pin design.
EPROM is an electrically programmable memory which has been available for about 30 years since its first inception in 1980. Its market size has shrunk and become very small. EPROM has been widely replaced by NOR flash in many applications due to the lack of in-system re-programmability. EPROM is commonly used in one-time-program (OTP) applications for code or BIOS storage. The byte or word program operation of EPROM uses a CHE scheme similar to NOR flash but the chip-erase operation relies entirely on an UV-light exposure scheme. Therefore, the chip erase operation can only be performed before the sealing of the package although the program operation can be done by the programmer after the sealing of the package. Currently, available EPROM density is below 4 Mb in both parallel read and serial read packages. The most advanced technology node in production used 0.5 um technology in 2010.
The mask programmable read only memory (ROM), which is commonly called as mask ROM is the only NVM memory that does not require any high voltage (HV) devices. It uses either boron or phosphorus implant mask for programming the code data in IC fab. It is the cheapest NVM storage solution without in-system and in-circuit re-programmability. The code data change process of mask ROM takes very long time with throughput of approximately one month. Typical ROM arrays have two popular types. The cell array configured in a serial string like a NAND array uses phosphorus-implant to program the threshold voltage (Vt) of the cell from +0.7 V (non-conducting) to about −2.0 V (conducting) for serial ROM designs, while the cell array configured in a parallel string like a NOR array preferably uses boron-implant to program the threshold voltage Vt from +0.7 V (conducting) to +4.0 V (non-conducting) for parallel ROM designs.
Currently, parallel ROM density has achieved about 512 Mb in high pin count packages with x8, x16 or x32 I/Os with multiple address pins for fast random access code storage. The most advanced technology node in production used 70 nm low voltage (LV) process in 2010.
In contrast, the different types of VM memories include DRAM, SRAM and pSRAM. Unlike NVM that allows both serial and parallel access, the most popular VM memories are offering random parallel access in both read and write operations. Both DRAM and pSRAM use the same capacitor charge cells that typically require periodic refreshing within 30 ms to prevent data loss due to junction leakage happened at n-active and p-substrate bipolar junction. Each SRAM cell is comprised of six CMOS transistors (6 T) which act like a latch and therefore there is no concern with the leakage of a DRAM cell. As a result, SRAM does not require any refreshing, consuming much less power than DRAM.
SRAM is the fastest random access VM memory. SRAM stands for static-random-access Memory. It has the largest cell size in all memories because each SRAM cell is comprised of six LV CMOS transistors including three PMOS and three NMOS devices being laid out in a much larger silicon area as compared to other VM or NVM memory cells.
Because SRAM is a large LV cell, its process can be made fully logic-compatible. In 2010, the highest available density of parallel SRAM was 64 Mb, which was made by 30 nm technology node. Parallel SRAM is being used as the high speed standalone or embedded cache memory with the fastest random access speed of read and write operations of 10 ns. The only disadvantage is its high cost and expensive unit selling price due to the required large cell size made on silicon area. As a result, the SRAM market size is not as big as pSRAM and DRAM. Currently, there are many types of SRAM available with very fast random read and write speed using comparable techniques.
DRAM stands for dynamic-random-access memory. One unique feature of DRAM is that it has the smallest cell size in all VM memories because each DRAM cell is only comprised of one LV CMOS transistor (1 T) along with one capacitor being laid out in a much smaller silicon area as compared to the large 6 T SRAM memory cell.
In 2010, the highest available density of parallel-DRAM is 4 Gb, which is made by 35 nm technology node. DRAM is being used as the extremely high density random access VM memory with the random access speed slower than regular SRAM but compatible with the speed of the regular NOR flash in the same density level. For example, the random access speed of read and write operations of 2 Gb parallel DRAM is around 70-100 ns about the same as the spec of 2 Gb parallel NOR in 2010.
The advantage of DRAM is its low cost and extremely high density but its disadvantage is the high current consumption due the required periodic refreshing cycles to prevent the loss of the data charge stored in each small capacitor node in each DRAM cell. Typically, the minimum required refreshing cycle time has to be within 30 ms, depending on the density level and operating temperature. At a higher temperature operating condition, the refreshing cycle time has to be shorten due to the higher junction leakage occurring at the bipolar junction node in each cell capacitor.
pSRAM, which stands for pseudo SRAM, has a core cell similar to a DRAM cell comprised of 1 T NMOS transistor and one capacitor. There are three major differences between SRAM and pSRAM. The first one is that all the memory cells of pSRAM need to be periodically refreshed but the operation is built and embedded on the memory chip and performed in a way fully transparent to system designs. As a result, pSRAM consumes much more power than SRAM.
The second one is that the random read and write speed of pSRAM is still slower than SRAM. The third one is the address pin assignment. In conventional SRAM memory, all memory addresses of rows and columns can be coupled from system at the same time because there are sufficient address and data pins available in a SRAM die. In contrast, pSRAM is similar to DRAM and its address pins have to be used as raw addresses (RAS) before the column addresses (CAS).
In the traditional high density random access VM memories (DRAM and pSRAM), the specs of read speed are comparable to the specs of write speed and are usually defined in the same ranges between 50-70 ns when the memory density reaches above 32 Mb. In contrast, the traditional high density random access NVM memories (NAND and NOR), the specs of read and write speed are quite different. The read speed usually falls below 100 ns but the write speed is in the ms range.
The normal write operation includes two major ones such as erase and program operations. For example, the random read speed for NAND flash is usually defined with a slow page read of 20 us along with a much faster random byte read or word read of around 10-15 ns. But according to the spec, NAND flash takes about 200 us to perform a SLC FN page program operation and a few ms to perform a reverse-FN block erase operation. While the random read speed of NOR is usually defined with a faster spec between 70-100 ns in a byte read or word read operation but takes about 5 us for a byte or word program operation and also a few hundred ms for a block (64 KB) erase or small sector (4 KB) erase operation. In some NOR flash memory designs, before the erase operation, a few ms pre-program operation is usually required to achieve better control over the undesired over-erase issue and to achieve more uniform erased Vt.
As explained above, the write speed gap of the traditional NVM NAND and NOR is one or two orders slower than the VM counter parts. The speed gap of byte or word random read operations between NVM NOR and VM SRAM or pSRAM is about 2 to 3 times. For example, the fastest NOR read speed can be around 20-30 ns, while the fastest read speed of SRAM can be around 10-15 ns in the density below 32 Mb under the same operating conditions of technology node, VDD voltage, temperature and output capacitance loading.
For the market applications using VM memory with required density higher than 64 Mb, the lower cost pSRAM and DRAM memories are commonly used to replace SRAM. The random access read speed of both pSRAM and DRAM is much slower than SRAM. Therefore, any improvement in random read speed over the existing pSRAM and DRAM has become important in the high density VM market.
At present day flash nonvolatile memories are divided into two major product categories including the faster random access asynchronous or synchronous NOR flash and the slower serial access synchronous NAND flash. The NOR flash nonvolatile memory as presently designed has a high pin count with multiple external address and data pins along with appropriate control signal pins. One disadvantage of the NOR flash is that as the density is doubled, the number of its required external pin count increases by one.
In contrast, NAND flash has an advantage of having a smaller pin count than NOR flash with no address input pins or with 16 address pins (A0-A15) in some special NAND products. As density increases, the NAND flash pin count is always kept constant. Both main-streamed NAND flash and NOR flash nonvolatile memory today have incompatible technology process, But both cell structures in production at the present time use similar one charge retaining (charge storage or charge trapping) transistor memory cell that stores one bit of data as charge and is commonly referred to as a single-level program cell (SLC). They are respectively referred as one-bit/one transistor NAND cell or NOR cell, storing a single-level programmed data in one physical bit cell.
Both NAND and NOR flash nonvolatile memories provide the advantage of in-system and in-circuit program and erase capabilities and have a specification for providing at least 100K endurance cycles. In addition, both single-chip NAND and NOR flash nonvolatile memory products can provide giga-bit density because of their highly-scalable cell sizes. Currently, the highest density single chip double polycrystalline silicon gate NAND flash nonvolatile memory chip is 64 Gb. In contrast, a double polycrystalline silicon gate NOR flash nonvolatile memory chip has a density of 2 Gb.
The big gap between NAND and NOR flash nonvolatile memory density is a result of the superior scalability of NAND flash nonvolatile memory cell over a NOR flash nonvolatile memory. A NOR flash nonvolatile memory cell requires 5.0 V drain-to-source (Vds=5.0 V) to enable a high current CHE injection program. Alternately, a NAND flash nonvolatile memory cell requires Vds=0 V between the drain and the source for a low current Fowler-Nordheim channel tunneling program process. As a result, one NAND flash cell occupies only one half area of a one NOR flash cell. This permits a NAND flash nonvolatile memory device to be used in low cost applications that require huge data storage, while the NOR flash device is extensively used as a program-code storage memory which requires less data storage but faster random access speed now.
However, there is still a need to improve the speed of the slow NAND flash in the market place. For example, the current consumer portable applications require a high speed, high density, and low cost nonvolatile memory solution. The “Open NAND Flash Interface Specification”, Revision 2.3, Aug. 25, 2010, by the Open NAND Flash Interface working group (ONFI) defines a standardized NAND flash device interface and protocol for providing the way for a system to be designed to support a range of NAND flash devices without direct design pre-association. The ONFI interface provides support for a range of device capabilities and future development of NAND nonvolatile memory devices.
The ONFI interface supports asynchronous and synchronous operations and the ONFI working group has proposed many powerful functions such as “EZ NAND”. The “EZ NAND” includes the control logic packaged together with NAND to perform the NAND management functionality that is lithography specific (e.g. ECC), while retaining the NAND protocol infrastructure. The ONFI interface does not consider memory structures that combine NAND memory arrays with NOR memory arrays on a single substrate. Further, ONFI interface is not proposed to be used for fast random and extremely high density NOR usage either.
The ONFI NAND interface definition has two options including x8 and x16 I/O pins for respective byte and word data access with full compatibility in pin definition and pin number. Besides newly proposed ONFI NAND, several popular NAND-like flash memories are also available in the market places. For example, the conventional NAND flash with its own 48 pin definition has been extensively used in the market place for more than a decade. The regular NAND has both x8 and x16 I/O pin options.
Another popular flash is SLC OneNAND which was introduced by Samsung for years. The highest density of OneNAND was 8 Gb in 2010 with additional 16 address pins of A0-A15 on a 48 pin NAND-like package. The OneNAND made of NAND flash along with several fast cache memories on a same die is used as a pseudo NOR solution with 48 pins as the regular NAND flash. OneNAND has the advantage over the traditional NOR flash when density gets higher than 2 Gb. However, the 16 only independent address pins confine the full random access space to a page, rather than a byte or a word. As a consequence, OneNAND is a pseudo NOR with random page access, rather than random byte or random word access NVM memory. It is also desirable to improve the speed of operation for the OneNAND flash memory.